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<!@TC:1498605988>
#Build: Synplify Pro L-2016.09L+ice40, Build 077R, Dec  2 2016
#install: C:\lscc\iCEcube2.2017.01\synpbase
#OS: Windows 8 6.2
#Hostname: LAPOT

# Wed Jun 28 02:26:28 2017

#Implementation: switch_test_Implmnt

<a name=compilerReport1></a>Synopsys HDL Compiler, version comp2016q3p1, Build 141R, built Dec  5 2016</a>
@N: : <!@TM:1498605989> | Running in 64-bit mode 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

<a name=compilerReport2></a>Synopsys Verilog Compiler, version comp2016q3p1, Build 141R, built Dec  5 2016</a>
@N: : <!@TM:1498605989> | Running in 64-bit mode 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.

@I::"C:\lscc\iCEcube2.2017.01\synpbase\lib\generic\sb_ice40.v" (library work)
@I::"C:\lscc\iCEcube2.2017.01\synpbase\lib\vlog\hypermods.v" (library __hyper__lib__)
@I::"C:\lscc\iCEcube2.2017.01\synpbase\lib\vlog\umr_capim.v" (library snps_haps)
@I::"C:\lscc\iCEcube2.2017.01\synpbase\lib\vlog\scemi_objects.v" (library snps_haps)
@I::"C:\lscc\iCEcube2.2017.01\synpbase\lib\vlog\scemi_pipes.svh" (library snps_haps)
@I::"D:\Drive\Projects\Lattice FPGA\Projects\switch_test\top.v" (library work)
Verilog syntax check successful!
Selecting top level module top
@N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="D:\Drive\Projects\Lattice FPGA\Projects\switch_test\top.v:1:7:1:10:@N:CG364:@XP_MSG">top.v(1)</a><!@TM:1498605989> | Synthesizing module top in library work.


At c_ver Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 69MB peak: 71MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Jun 28 02:26:29 2017

###########################################################]
<a name=compilerReport3></a>Synopsys Netlist Linker, version comp2016q3p1, Build 141R, built Dec  5 2016</a>
@N: : <!@TM:1498605989> | Running in 64-bit mode 
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="D:\Drive\Projects\Lattice FPGA\Projects\switch_test\top.v:1:7:1:10:@N:NF107:@XP_MSG">top.v(1)</a><!@TM:1498605989> | Selected library: work cell: top view verilog as top level
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="D:\Drive\Projects\Lattice FPGA\Projects\switch_test\top.v:1:7:1:10:@N:NF107:@XP_MSG">top.v(1)</a><!@TM:1498605989> | Selected library: work cell: top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Jun 28 02:26:29 2017

###########################################################]
@END

At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Jun 28 02:26:29 2017

###########################################################]
<a name=compilerReport4></a>Synopsys Netlist Linker, version comp2016q3p1, Build 141R, built Dec  5 2016</a>
@N: : <!@TM:1498605991> | Running in 64-bit mode 
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="D:\Drive\Projects\Lattice FPGA\Projects\switch_test\top.v:1:7:1:10:@N:NF107:@XP_MSG">top.v(1)</a><!@TM:1498605991> | Selected library: work cell: top view verilog as top level
@N:<a href="@N:NF107:@XP_HELP">NF107</a> : <a href="D:\Drive\Projects\Lattice FPGA\Projects\switch_test\top.v:1:7:1:10:@N:NF107:@XP_MSG">top.v(1)</a><!@TM:1498605991> | Selected library: work cell: top view verilog as top level

At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime

Process completed successfully.
# Wed Jun 28 02:26:31 2017

###########################################################]
Pre-mapping Report

# Wed Jun 28 02:26:31 2017

<a name=mapperReport5></a>Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1612R, Built Dec  5 2016 10:31:39</a>
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.09L+ice40

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)

@A:<a href="@A:MF827:@XP_HELP">MF827</a> : <!@TM:1498605993> | No constraint file specified. 
@L: D:\Drive\Projects\Lattice FPGA\Projects\switch_test\switch_test_Implmnt\switch_test_scck.rpt 
Printing clock  summary report in "D:\Drive\Projects\Lattice FPGA\Projects\switch_test\switch_test_Implmnt\switch_test_scck.rpt" file 
@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1498605993> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1498605993> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 102MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 101MB peak: 103MB)

ICG Latch Removal Summary:
Number of ICG latches removed:	0
Number of ICG latches not removed:	0
syn_allowed_resources : blockrams=18  set on top level netlist top

Finished netlist restructuring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)



<a name=mapperReport6></a>Clock Summary</a>
*****************

Start     Requested     Requested     Clock     Clock     Clock
Clock     Frequency     Period        Type      Group     Load 
---------------------------------------------------------------
===============================================================

Finished Pre Mapping Phase.
@N:<a href="@N:BN225:@XP_HELP">BN225</a> : <!@TM:1498605993> | Writing default property annotation file D:\Drive\Projects\Lattice FPGA\Projects\switch_test\switch_test_Implmnt\switch_test.sap. 

Starting constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)

None
None

Finished constraint checker (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)

Pre-mapping successful!

At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 46MB peak: 133MB)

Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Wed Jun 28 02:26:33 2017

###########################################################]
Map & Optimize Report

# Wed Jun 28 02:26:33 2017

<a name=mapperReport7></a>Synopsys Lattice Technology Mapper, Version maplat, Build 1612R, Built Dec  5 2016 10:31:39</a>
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
Product Version L-2016.09L+ice40

Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)

@N:<a href="@N:MF248:@XP_HELP">MF248</a> : <!@TM:1498605997> | Running in 64-bit mode. 
@N:<a href="@N:MF666:@XP_HELP">MF666</a> : <!@TM:1498605997> | Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.) 

Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)


Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 101MB)


Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 103MB)



Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)


Available hyper_sources - for debug and ip models
	None Found

@N:<a href="@N:MT206:@XP_HELP">MT206</a> : <!@TM:1498605997> | Auto Constrain mode is enabled 

Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)


Starting factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)


Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 131MB peak: 133MB)


Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)


Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)


Starting Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)


Finished Early Timing Optimization (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)


Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)


Finished preparing to map (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)


Finished technology mapping (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
   1		0h:00m:01s		100000.00ns		  17 /         0

Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)


Finished restoring hierarchy (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 131MB peak: 133MB)



@S |Clock Optimization Summary


<a name=clockReport8></a>#### START OF CLOCK OPTIMIZATION REPORT #####[</a>

0 non-gated/non-generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
0 instances converted, 0 sequential instances remain driven by gated/generated clocks



##### END OF CLOCK OPTIMIZATION REPORT ######]


Start Writing Netlists (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 106MB peak: 133MB)

Writing Analyst data base D:\Drive\Projects\Lattice FPGA\Projects\switch_test\switch_test_Implmnt\synwork\switch_test_m.srm

Finished Writing Netlist Databases (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 130MB peak: 133MB)

Writing EDIF Netlist and constraint files
@N:<a href="@N:BW103:@XP_HELP">BW103</a> : <!@TM:1498605997> | The default time unit for the Synopsys Constraint File (SDC or FDC) is 1ns. 
@N:<a href="@N:BW107:@XP_HELP">BW107</a> : <!@TM:1498605997> | Synopsys Constraint File capacitance units using default value of 1pF  
@N:<a href="@N:FX1056:@XP_HELP">FX1056</a> : <!@TM:1498605997> | Writing EDF file: D:\Drive\Projects\Lattice FPGA\Projects\switch_test\switch_test_Implmnt\switch_test.edf 
L-2016.09L+ice40

Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 131MB peak: 133MB)


Start final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 132MB peak: 133MB)



<a name=timingReport9></a>##### START OF TIMING REPORT #####[</a>
# Timing Report written on Wed Jun 28 02:26:37 2017
#


Top view:               top
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N:<a href="@N:MT320:@XP_HELP">MT320</a> : <!@TM:1498605997> | This timing report is an estimate of place and route data. For final timing results, use the FPGA vendor place and route report. 

@N:<a href="@N:MT322:@XP_HELP">MT322</a> : <!@TM:1498605997> | Clock constraints include only register-to-register paths associated with each individual clock. 



<a name=performanceSummary10></a>Performance Summary</a>
*******************


Worst slack in design: NA






<a name=clockRelationships11></a>Clock Relationships</a>
*******************

Clocks            |    rise  to  rise   |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
--------------------------------------------------------------------------------------------------------
Starting  Ending  |  constraint  slack  |  constraint  slack  |  constraint  slack  |  constraint  slack
--------------------------------------------------------------------------------------------------------
========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



<a name=interfaceInfo12></a>Interface Information </a>
*********************

No IO constraint found


##### END OF TIMING REPORT #####]

Timing exceptions that could not be applied
None

Finished final timing analysis (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 132MB peak: 133MB)


Finished timing report (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 132MB peak: 133MB)

---------------------------------------
<a name=resourceUsage13></a>Resource Usage Report for top </a>

Mapping to part: ice5lp2ksg48
Cell usage:
SB_CARRY        7 uses
SB_LUT4         9 uses

I/O ports: 18
I/O primitives: 18
SB_IO          18 uses

I/O Register bits:                  0
Register bits not including I/Os:   0 (0%)
Total load per clock:

@S |Mapping Summary:
Total  LUTs: 9 (0%)

Distribution of All Consumed LUTs = LUT4 
Distribution of All Consumed Luts 9 = 9 

Mapper successful!

At Mapper Exit (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 26MB peak: 133MB)

Process took 0h:00m:04s realtime, 0h:00m:03s cputime
# Wed Jun 28 02:26:37 2017

###########################################################]

</pre></samp></body></html>
